The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device with a duty correction circuit, which can improve the reliability of the device by controlling the duty ratio of a clock signal used as a reference of operation.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells selected by addresses inputted together with the data.
As the operating speed of the system is increasing, the data processor requires the semiconductor memory device to input and output data at higher speed. For the purpose of high-speed data input and output, a synchronous memory device was developed. The synchronous memory device inputs and outputs data in synchronization with a system clock. However, because even the synchronous memory device could not meet the required data input/output speed, a double data rate (DDR) synchronous memory device was developed. The DDR synchronous memory device outputs or inputs data at falling edges and rising edges of the system clock. The DDR synchronous memory device must process two data during one cycle of the system clock so as to input and output data at a falling edge and a rising edge of the system clock. Specifically, the DDR memory device must output data exactly in synchronization with the rising edge and the falling edge of the clock signal. To this end, a data output circuit of the DDR memory device outputs data in synchronization with rising and falling edges of the system clock.
However, the system clock inputted to the semiconductor memory device is inevitably delayed when it arrives at a data output circuit because it passes through a clock input buffer, a clock transmission line, and so on. In addition, the system clock may be distorted by a variety of delay elements within the semiconductor memory device. Thus, if the data output circuit outputs data in synchronization with the delayed system clock, an external device will receive data that are not synchronized with rising edges and falling edges of the system clock.
To solve this problem, the semiconductor memory device uses a delay locked loop (DLL) for locking a delay of the clock signal, and a duty correction circuit for correcting a duty ratio of the clock signal. More specifically, the DLL compensates for a delay caused by internal circuits of the memory device until the system clock as it is inputted to the memory device is accurately transferred to the data output circuit. The duty correction circuit corrects the duty ratio of a clock signal inputted to or outputted from the DLL, or the duty ratio of a clock signal used for transferring data to the inside or outside of the semiconductor memory device. Since a high-speed semiconductor memory device inputs or outputs data or addresses at both the rising edges and the failing edges of the clock signal, a malfunction may occur due to an insufficient clock margin for an entire operation of the semiconductor memory device or the device may not perform required operations within a predefined time when there is a difference between a clock rising timing and a clock falling timing, that is, a high level duration and a low level duration of the clock signal.
In order to correct the duty ratio of the clock signal, the duty correction circuit must measure the duty ratio of the clock signal and adjust the duty ratio by delaying the clock signal. In this case, if there occurs an error in measuring the duty ratio, the duty correction circuit may malfunction to a degree of the error. However, as the semiconductor memory device becomes even more highly integrated and operates at higher speed, the error occurring in measuring the duty ratio is not negligible. Specifically, as the critical dimension (CD) of the semiconductor memory device is scaled down, the error may increase. On the other hand, when the period of the external clock signal decreases, an error ratio may further increase. The error ratio represents an error value with respect to the period of the clock signal. The increase of the error ratio means that the operation margin decreases in the read or write operation making it less likely the correct operation can be achieved within the given time. The increase of the error ratio may degrade the reliability of the semiconductor memory device.